`timescale 1ns / 1ps



module tbcounter;

	// Inputs
	reg clk;
	reg [3:0] timeIn;
	reg start_timer;
	// Outputs
	wire [3:0] timeOut;
	wire expired;

	// Instantiate the Unit Under Test (UUT)
	timer uut (
		.clk(clk), 
		.start_timer(start_timer),
		.timeIn(timeIn), 
		.timeOut(timeOut), 
		.expired(expired)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		timeIn=4'd15;
		start_timer=1;
		#1000
		start_timer=0;
		#1000
		start_timer=1;
		#1000
       start_timer=0;
		// Add stimulus here

	
	end
	// Clock generator
	always begin
     #20
	  clk = !clk; // 
	end
      
endmodule

